1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to high-speed data output related circuits for synchronous semiconductor memory devices.
2. Description of the Related Art
To reduce the operating cycle time and increase the operating speed of a memory device, data read from a memory cell should be transmitted quickly to an output terminal through a sense amplifier and data output buffer without any signal margin or delay. However, efforts to reduce of the cycle time have been limited by input/output speed differences, power supply voltages, signal margins due to effects such as temperature, separate control of sensing and data latch operations, and the like.
FIGS. 1a and 1b together illustrate a general data output related circuit which includes a read path and a data output scheme for a general synchronous static random access memory device. A main sense amplifier 100 senses data received from memory cells through the read path. A level shifter 20 converts the sensed data to a CMOS level. A data output buffer 30 latches output data from the level shifter 20 and transmits the latched output data to an output terminal. An off-chip driver 400 transmits final data out of the chip. The level shifter 20 converts signals from the level provided from the sense amplifier 100 to a predetermined level, for example, the CMOS level. The level shifter 20, the data output buffer 30 and the off-chip driver 400 are elements commonly utilized in output circuits and other circuits within a semiconductor memory device.
FIG. 2 is a simulation timing chart illustrating the operation of the circuit of FIGS. 1a and 1b. When an enable signal MSAEN for enabling the main sense amplifier 100 is enabled, there occurs a potential difference between the output signals SAS and SASB of the main sense amplifier 100. When an enable signal KDPRECB for enabling the level shifter 20 is enabled to logic "LOW", level shifted data DATAA and DATAAB, which have been precharged to logic "LOW", arc set to logic "HIGH" and "LOW", respectively, as shown by arrow as 1. When a signal KPDATA is enabled by an external clock buffer, the data output buffer 30 transmits the data DATAA and DATAAB to nodes NO3 and NO4 where they are latched as data DATAB and DATABB, respectively. This data latch operation is performed by an inverter latch consisting of inverters 40 and 41 each having an input terminal coupled to the other's output terminal. During the next cycle, when a signal KDATA is applied to the circuit, the data output buffer 30 is enabled. The latched data DATAB and DATABB are transmitted to nodes N05 and N06 where they are latched as data DATAC and DATACB, respectively. The latched data DATAC and DATACB are transmitted to an output terminal I/O through a node NOQ when an output enable signal OE is supplied from an external source such as a microprocessor.
During a data read operation of the data output related circuit of FIGS. 1a and 1b, the sensing operation of the main sense amplifier 100, the level conversion operation of the level shifter 20, and the latch operation for latching the level shifted data in the data output buffer 30 have separate timing, and are controlled by control signals supplied from a clock buffer within the device. This is a disadvantage because the external control signals must be uniformly applied at times that depend on factors such as the input/output speed difference, the power supply voltage, the signal margin which depends on effects such as variations in temperature, variations in pulse widths, etc. These factors make it difficult to reduce the operating cycle time of the memory device because the worst case values of all the factors must be considered when applying the external control signals. Therefore, it is difficult to increase the operating speed of the memory device due to the limitations in reducing the cycle time.